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Computer organization Notes

Counters

Counter is a sequential circuit. A digital circuit which is used for counting pulses is known as counter. Counters are the digital device which performs binary counting. It is very useful and important sub-system of a digital system. Counters are found in almost all the equipments containing digital logic. They are used for counting the number of occurrences of an event. They are very useful for generating timing signal to control the sequence of operation. In a digital computer counter is a register which is capable of counting the number of pulses of a clock that arrive at its clock input. They may be used for measurement of frequency, time and speed etc. A counter circuit normally uses flip-flops with complement capability. Counter is the widest application of flip-flops. Counters may be used to count up or down, to cycle through memory addresses in microprocessors applications, to generate waveform of particular patterns and frequencies, and to activate other logic circuits in a complex process. Counters are of two types.
• Asynchronous or ripple counters.
• Synchronous counters.
Main difference between both these counter types is in the triggering conditions for them. In synchronous counters same clock pulse is applied to all the flip-flops in the counter and all flip-flops are triggered simultaneously. In asynchronous counters, the clock pulse is applied only to the first flip-flop and all other flip-flops are triggered by the output of the flip-flop proceeding it.
Asynchronous Counter
It is one of the basic and simple counters which are not commonly used but it is having the limitation of speed of operation. These counters are also known as Ripple counters or serial counters. Here the delay time of all the flip-flops are added. Here different clock pulses are used for different flip-flops. In an asynchronous counter, an external event is used to directly SET or CLEAR a flip-flop when it occurs. An n-bit ripple counter can count up to a maximum of 2n states.
In this type of counter the output of one flip-flop serve as a source for triggering of a next flip-flop. Here each flip-flop is triggered by the previous flip-flop and due to this type of combination these counters have cumulative settling time and their overall speed is low. The frequency in asynchronous counter is higher than synchronous counters. A number of logic devices are needed for the operation of asynchronous counter. These counters are more costly than synchronous counter. These counters have an overall count which ripples through, meaning the overall operation is relatively slow. They require virtually no design.
Let us consider a 4-bit ripple counter which is capable of counting 16 counts and after the 16th count all flip-flops are immediately reset. Here the counter starts from beginning and clock pulse is applied to the flip-flop containing least significant bit. The circuit diagram, truth table and wave form chart for a 4-bit synchronous counter can be drawn as follows:

Waveform Chart for 4-bit Up counter.

Truth table for 4-bit Up counter.

This counter is called as ripple counter because the carry moves through the flip-flop like a ripple on the water. Here Q0 flip flop must toggle before Q1 which again must toggle before Q2 and Q2 must toggle before Q3. In this counter worst case occurs when word changes from 0111 to 1000.
4-bit Asynchronous Down Counter

Waveform Chart for 4-bit down counter.

Truth table for 4-bit down counter.

Asynchronous counters are used as frequency dividers, as divide by N counters. These are used for low power applications and low noise emission. These are used in designing asynchronous decade counter. Also used in Ring counter and Johnson counter. Asynchronous counters are used in Mod N ripple counters. EX: Mod 3, Mod 4, Mod 8, Mod 14, Mod 10 etc.
Advantages of Asynchronous Counters:
• Asynchronous Counters can easily be made from Toggle or D-type flip-flops.
• They are called “Asynchronous Counters” because the clock input of the flip-flops are not all driven by the same clock signal.
• Each output in the chain depends on a change in state from the previous flip-flops output.
• Asynchronous counters are sometimes called ripple counters because the data appears to “ripple” from the output of one flip-flop to the input of the next. And they are used in low-speed circuits.
• They can be implemented using “divide-by-n” counter circuits which divide the input by n, where n is an integer
• Truncated counters can produce any modulus number count.
• Asynchronous counters are also used as Truncated counters. These can be used to design any mod number counters, i.e. even Mod (ex: mod 4) or odd Mod (ex: mod3).
Disadvantages of Asynchronous Counters:
• An extra “re-synchronizing” output flip-flop may be required.
• To count a truncated sequence not equal to 2n, extra feedback logic is required.
• Counting a large number of bits, propagation delay by successive stages may become undesirably large.
• Counting errors occur at high clocking frequencies.
• This delay gives them the nickname of “Propagation Counters”.
• Synchronous Counters are faster and more reliable as they use the same clock signal for all flip-flops.
Asynchronous Up-Down Counters
By adding up the ideas of UP counter and DOWN counters, we can design asynchronous up /down counter. In certain applications a counter must be able to count both up and down. The circuit below is a 3-bit up-down counter. It counts up or down depending on the status of the control signals UP and DOWN. When the UP input is at 1 and the DOWN input is at 0, the NAND network between FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of FF1. Similarly, Q of FF1 will be gated through the other NAND network into the clock input of FF2. Thus the counter will count up. The 3 bit asynchronous up/ down counter is shown below.

It can count in either ways, up to down or down to up, based on the clock signal input.
UP Counting
If the UP input and down inputs are 1 and 0 respectively, then the NAND gates between first flip flop to third flip flop will pass the non inverted output of FF 0 to the clock input of FF 1. Similarly, Q output of FF 1 will pass to the clock input of FF 2. Thus the UP /down counter performs up counting.
DOWN Counting
If the DOWN input and up inputs are 1 and 0 respectively, then the NAND gates between first flip flop to third flip flop will pass the inverted output of FF 0 to the clock input of FF 1. Similarly, Q output of FF 1 will pass to the clock input of FF 2. Thus the UP /down counter performs down counting.
The up/ down counter is slower than up counter or a down counter, because the addition propagation delay will added to the NAND gate network
Synchronous Counters
The counters which use clock signal to change their transition are called “Synchronous counters”. This means the synchronous counters depends on their clock input to change state values. In synchronous counters, all flip flops are connected to the same clock signal and all flip flops will trigger at the same time.
There are many types of synchronous counters available in digital electronics. They are listed below.
• 4 bit synchronous UP counter
• 4 bit synchronous DOWN counter
• 4 bit synchronous UP / DOWN counter
• Ring counters
• Johnson counters etc.
4 bit Synchronous UP Counter
The 4 bit up counter shown in below diagram is designed by using JK flip flop. External clock pulse is connected to all the flip flops in parallel. For designing the counters JK flip flop is preferred .The significance of using JK flip flop is that it can toggle its state if both the inputs are high, depending on the clock pulse. The inputs of first flip flop are connected to HIGH (logic 1), which makes the flip flop to toggle, for every clock pulse entered into it. So the synchronous counter will work with single clock signal and changes its state with each pulse.
The most important advantage of synchronous counters is that there is no cumulative time delay because all flip-flops are triggered in parallel. Thus, the maximum operating frequency for this counter will be significantly higher than for the corresponding ripple counter.
The J and K inputs of FFA are connected to HIGH. FFB has its J and K inputs connected to the output of FFA, and the J and K inputs of FFC are connected to the output of an AND gate that is fed by the outputs of FFA and FFB, and the J and K inputs of FFD are connected to the output of an AND gate that is fed by the outputs of FFA, FFB and FFC.

Waveform Chart for 4-bit down counter.

Truth table for 4-bit down counter.

4 bit Synchronous DOWN Counter
Down counter counts the numbers in decreasing order. This is similar to an up counter but is should decrease its count. So inputs of JK flip- flop are connected to the inverted Q (Q’) .The 4 bit down counter shown in below diagram is designed by using JK flip flop. The same external clock pulse is connected to all the flip flops.

As the counter has to count down the sequence, initially all the inputs will be in high state as they have to count down the sequence. It will start with 1111 and ends with 0000, similar to the up counter.
In the down counter it should be remembered that, preceding flip flop will toggles only if front flip flop produces low logic at its output.
4 bit Synchronous Up/Down Counter
The above two counters can be implemented in a single counter called up down counter. This can be selected from its input. The design of up/ down counter with JK flip flops is shown below.

The up/ down counter has “Up” and “Down” count modes by having 2 input AND gates, which are used to detect the appropriate bit conditions for counting operation. OR gates are used to combine the outputs of AND gate, from each JK flip flop.
We provide a up/ down control line which enables upper or lower series of AND gates to pass the outputs of JK flip flops, Q , Q’ to the next stage of flip flop, in the cascaded arrangement.
If the up /down control line is set to HIGH, then the top AND gates are in enable state and the circuit acts as UP counter. If the up /down control line is set to low, then the bottom AND gates are in enable state and the circuit acts as DOWN counter.
Then to summarise some of the main points about Synchronous Counters:
• Synchronous Counters can be made from Toggle or D-type flip-flops.
• Synchronous counters are easier to design than asynchronous counters.
• They are called synchronous counters because the clock input of the flip-flops are all clocked together at the same time with the same clock signal.
• Due to this common clock pulse all output states switch or change simultaneously.
• With all clock inputs wired together there is no inherent propagation delay.
• Synchronous counters are sometimes called parallel counters as the clock is fed in parallel to all flip-flops.
• The inherent memory circuit keeps track of the counters present state.
• The count sequence is controlled using logic gates.
• Overall faster operation may be achieved compared to Asynchronous counters




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