Discussion Forum

Interative Forum for discussing any query literally to UGC-NET Computer Science, GATE Computer Science and Computer Sciene and Technology in general.

ugc_net image

UGC-NET Computer Science

Correspondence Courses and Test Series to prepare for UGC-NET computer science and applications

GATE image


MCQs, Lecture Notes, Ebooks for GATE preparation

freestuff image
jobs image

Jobs Newsfeed

Timely information of various Recruitments.


Computer organization Notes


A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs. Decoder is identical to a de-multiplexer without any data input. It performs operations which are exactly opposite to those of an encoder. a decoder is a combinational logic circuit that converts a binary integer value to an associated pattern of output bits. They are used in a wide variety of applications, including data de-multiplexing, seven segment displays, and memory address decoding.
There are several types of binary decoders, but in all cases a decoder is an electronic circuit with multiple input and multiple output signals, which converts every unique combination of input states to a specific combination of output states. Decoder is a combinational circuit that converts a binary input of n variables into maximum of 2n unique output variables. Such decoders are called n-to-m decoders where m<=2n. Decoders can detect a code and activate a single output to signal the presence of that code. Decoders have many applications, from producing system alerts in alarm systems to performing the task of driving multiple devices in microprocessor systems. Examples of Decoders are Code converters, BCD to seven segment decoders, Nixie tube decoders, Relay actuator etc. The Block diagram of a general decoder can be drawn as follows:

In its general form, a decoder has N input lines to handle N bits and form one to 2N output lines to indicate the presence of one or more N-bit combinations. Let us consider the case of 3-bit binary decoder. In order to decode all possible combination of three bits, eight (23=8) decoding logic gates are required. This type of decoder is called the 3-line-to-8-line decoder because there are 3 inputs and 8 outputs. Let us consider the design of such a decoder such that for any given input combination the decoder output ‘1’. In a 3-to-8 decoder, three inputs are decoded into eight outputs. It has three inputs as A, B, and C and eight outputs from Y0 through Y7. Based on the combinations of the three inputs, only one of the eight outputs is selected. Enable input is provided to activate the decoded output depends on the input combinations A, B, and C. Suppose if A = B =1 and C= 0, then the output D6 is 1 and all other outputs are zero. For this purpose let us consider following table which lists the decoding functions and truth table for the 3 to 8 line decoder.
Decoding functions and truth table for the 3-line-to-8-line decoder

So from the truth table, min terms represents the each output equation and are given as
Using the above min term expressions for each output, the circuit of 3-to-8 decoder is can be implemented by using three NOT gates and eight AND gates. Each NOT gate provides the complement of the input and AND gates generates one of the min terms. Also enable input activate the decoded output depends on the input data. The logic diagram of this decoder is shown below.
Only one of eight outputs is high at a given time for a particular input combination, that why this decoder is also called as 1-of-8 decoder. Suppose, when ABC = 011, then only AND gate 4 has all inputs high, thus Y3 is high. Also, 3-bit binary numbers at the input is converted to eight digits at the output (which is equivalent to octal number system), that’s how; it is also called as a binary-to-octal decoder.

It is also possible represent the each output equation using max terms. In such case, inversion operation is performed in the logic circuit than that of circuit with min terms. The figure below shows the truth table of 3-to-8 line decoder using NAND gates. Each output in the table gives a max term representation. At a given time only one output is low and all other outputs will be high. For example, when A=B= 1 and C=0, then the output Y6 is zero and all other outputs are high as shown in below figure.

From the above table, a 3-to-8 line decoder is designed by using three NAND gates and three NOT gates. NOT gates generate the complement of input while the NAND gates generate max terms of each output as shown in below figure.

We can also use block diagram to represent 3-to-8 decoder as given below.

You can obtain Printed Copies of this material by making a request at with a nominal print charges.


Return To Computer organization Topics