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Computer organization Notes

Instruction Cycle

An instruction cycle (sometimes called a fetch–decode–execute cycle or fetch and execute cycle) is the basic operational process of a computer. It is the time period during which a computer reads and processes a machine language instruction from its memory or the sequence of actions that the central processing unit (CPU) performs to execute each machine code instruction in a program. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction dictates, and carries out those actions. A program residing in the memory unit of the computer consists of a sequence of instructions. The program is executed in the computer by going through a cycle for each instruction. Each instruction cycle in turn is subdivided into a sequence of subcycles or phases. Each computer’s CPU can have different cycles based on different instruction sets. In the basic computer each instruction cycle consists of the following phases:
1. Fetch: Read the next instruction from memory into the CPU.
2. Decode: Decode the instruction and interpret the opcode.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute: Perform the indicated instruction.

1. Fetch the instruction from main memory and Decode
Initially, the program counter PC is loaded with the address of the first instruction in the program. The sequence counter SC is cleared to 0, providing a decoded timing signal To. After each clock pulse, SC is incremented by one, so that the timing signals go through a sequence T0, T1, T2, and so on. The micro operations for the fetch and decode phases can be specified by the following register transfer statements.
T0: AR <-- PC
T1: IR <--M[AR], PC <-- PC + 1
T2: D0, • • • , D7 <-- Decode IR(12-14), AR <-- IR(0-11), I <-- IR(l5)
• At timing signal T0, address from PC is transferred to the address register AR.
• At timing signal T1, The instruction is read from memory location specified by address stored in AR and is placed in register IR. At the same time, PC is incremented by one to prepare it for the address of the next instruction in the program.
• At timing signal T2, the operation code in IR is decoded to find out the operation to be performed, the mode bit is transferred to flip-flop I, that will be used to find whether it is a case of direct or indirect address, and the address part of the instruction is transferred to AR.
Note that SC is incremented after each clock pulse to produce the sequence To, T1, and T2.
2. Determine the Type of Instruction
The timing signal that is active after the decoding is T3. During time T3, the control unit determines the type of instruction that was just read from memory. At this point bits I and D7 are checked. Type of instruction is determined as follows:
• If value of D7 is 1, the instruction is either a register-reference or input-output type and if D7 = 0, the operation code must be one of the other seven values 000 through 110, specifying a memory-reference instruction.
• if D7 = 1, Control then inspects the value of the first bit of the instruction i.e. Mode bit. Mode bit 1 means instruction is Input/Output and mode bit 0 means instruction type is register reference.
• If instruction is Memory reference instruction, mode bit is used to determine whether it is a direct address or indirect address. Mode bit 0 means the instruction is direct address and 1 means the instruction is Indirect address. Read the effective address from main memory if the instruction has an indirect address. Fetch requires data from main memory to be processed and placed into registers.
The whole process of fetching, decoding and determining the type of instruction is shown in the following flowchart.

Different types of instructions are determined by following different paths and the selected operations are activated at timing signal T3. The three instruction types are subdivided into four separate paths. The selected operation is activated with the clock transition associated with timing signal T3. This can be symbolized as follows:
D7’ IT3: AR  M [AR]
D7’ I'T3: Nothing
D7 I'T3: Execute a register-reference instruction
D7IT3: Execute an input-output instruction
Here D7’ and I’ means their value is 0. Sequence counter value changes with every timing signal. It is either incremented or is set to 0.




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