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Instruction Sets

An instruction set is a group of commands for a CPU in machine language. The term can refer to all possible instructions for a CPU or a subset of instructions to enhance its performance in certain situations. It includes the complete collection of instruction that are understood by a CPU. An instruction set enhances the performance of a CPU in certain situations. It can be considered as functional specification for a CPU. Actually implementing the CPU is equivalent to implementing the machine instruction set. All processors have some instructions for simple operations like read, write, move and also for complex operations where multiple memory accesses data transfer is required.
An Instruction set is a part of computer architecture. It is an interface between a computer’s software and its hardware, and thereby it enables the independent development of these two most important components of a system. The main goals of an instruction set are to maximize performance, Minimize Cost and Reduce design time.
There exist a number of ways to implement any instruction set. All types of implementations provide similar programming model and are able to run same set of binary executable code. Different implementation methods give a trade-offs between cost, performance, power consumption, size etc. Instruction sets are mainly implemented as:
• Hardwired
• Micro programmed
Hardwired design includes blocks of hard-wired electronic circuitry such as adder, multiplexer, counter, registers and ALUs etc. register transfer language is used for decoding and sequencing of each instruction set. Some designs use a combination of hardwired design and microcode for implementing the instruction set.
Computer Instructions
The basic computer has three instruction code formats, as shown in Figure below. Each format has 16 bits. The operation code (op-code) part of the instruction contains three bits and the meaning of the remaining 13 bits depends on the operation code encountered.
A memory-reference instruction uses 12 bits to specify an address. Here bit-number 0-11 are address bits and contain either direct or indirect address of operand in the memory. This is decided by most significant 15th bit I, known as mode bit. Here I is equal to 0 for direct address and to 1 for indirect address. The three bits 12-14 are used as operation code(values 000-110)
The register-reference instructions are recognized by the operation code 111 with a 0 in the leftmost bit (bit 15) of the instruction. A register-reference instruction specifies an operation on or a test of the AC register. An operand from memory is not needed; therefore, the other 12 bits are used to specify the operation or test to be executed because operands from memory are not used in these type of instruction.
Similarly, an input-output instruction does not need a reference to memory and is recognized by the operation code 111 with a 1 in the leftmost bit of the instruction. The remaining 12 bits are used to specify the type of Input-output operation or test performed

The type of instruction is recognized by the computer control from the four bits in positions 12 through 15 of the instruction. If the three op-code bits in positions 12 through 14 are not equal to 111, the instruction is a memory-reference type and the bit in position 15 is taken as the addressing mode I. There are 7 operations for memory reference instructions.
If the 3-bit op-code is equal to 111, control then inspects the bit in position 15. If this bit is 0, the instruction is a register-reference type. If the bit is 1, the instruction is an input-output type. Note that the bit in position 15 of the instruction code is designated by the symbol I but is not used as a mode bit when the operation code is equal to 111.
Only three bits o f the instruction are used for the operation code. It may seem that the computer is restricted to a maximum of eight distinct operations. However, since register-reference and input-output instructions use the remaining 12 bits as part of the operation code, the total number of instructions can exceed eight. In fact, the total number of instructions chosen for the basic computer is equal to 25.
The instructions for the computer are listed in Table below. The symbol designation is a three-letter word and represents an abbreviation intended for programmers and users. The hexadecimal code is equal to the equivalent hexadecimal number of the binary code used for the instruction.

Instruction Set Completeness
A computer should have a set of instructions so that the user can construct machine language programs to evaluate any function that is known to be computable. The set of instructions are said to be complete if the computer includes a sufficient number of instructions in each of the following categories:
1. Arithmetic, logical, and shift instructions
2. Instructions for moving information to and from memory and processor registers
3. Program control instructions together with instructions that check status conditions
4. Input and output instructions
Arithmetic, logical, and shift instructions provide computational capabilities for processing the type of data that the user may wish to employ. The bulk of the binary information in a digital computer is stored in memory, but all Computations are done in processor registers. Therefore, the user must have the capability of moving information between these two units. Decision making capabilities are an important aspect of digital computers. For example, Two numbers can be compared, and if the first is greater than the second, it may be necessary to proceed differently than if the second is greater than the first. Program control instructions such as branch instructions are used to change the sequence in which the program is executed. Input and output instructions are needed for communication between the computer and the user. Programs and data must be transferred into memory and results of computations must be transferred back to the user.
Computers may have instructions of several different lengths containing varying number of addresses. The number of address fields in the instruction format of a computer depends on the internal organization of its registers. Most computers fall into one of three types of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization.
Accumulator-type organization: All operations are performed with an implied accumulator register. The instruction format in this type of computer uses one address field. For example, the instruction that specifies an arithmetic addition is defined by an assembly language instruction as
ADD X
Where X is the address of the operand. The ADD instruction in this case results in the operation AC AC+M [X]. AC is the accumulator register and M [X] symbolizes the memory word located at address X.
General register type organization: The instruction format in this type of computer needs three register address fields. Thus the instruction for an arithmetic addition may be written in an assembly language as
ADD R1, R2, R3
to denote the operation R1<--R2 + R3. The number of address fields in the instruction can be reduced from three to two if the destination register is the same as one of the source registers.
Stack-type organization: Computers with stack organization would have PUSH and POP instructions which require an address field. Thus the instruction PUSH X will push the word at address X to the top of the stack. The stack pointer is updated automatically.
Operation-type instructions do not need an address field in stack-organized computers. This is because the operation is performed on the two items that are on top of the stack. The instruction ADD in a stack computer consists o f a n operation code only with no address field. This operation has the effect of popping the two top numbers from the stack, adding the numbers, and pushing the sum into the stack. There is no need to specify operands with an address field since all operands are implied to be in the stack.
Most computers fall into one of the three types of organizations that have just been described. Some computers combine features from more than one organizational structure.
Instruction Formats
A computer will usually have a variety of instruction code formats. It is the function of the control unit within the CPU to interpret each instruction code and provide the necessary control functions needed to process the instruction. The format of an instruction is usually depicted in a rectangular box symbolizing the bits of the instruction as they appear in memory words or in a control register. The bits of the instruction are divided into groups called fields. The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is determined.
The operation code field of an instruction is a group of bits that define various processor operations, such as add, subtract, complement, and shift. The bits that define the mode field of an instruction code specify a variety of alternatives for choosing the operands from the given address. Computers may have instructions of several different lengths containing varying number of addresses. The number of address fields in the instruction format of a computer depends on the internal organization of its registers.
Three-Address Instructions
Computers with three-address instruction formats can use each address field to specify either a processor register or a memory operand. The program in assembly language that evaluates X = (A + B)*(C + D) is shown below, together with comments that explain the register transfer operation of each instruction.

ADD R1, A, B			R1<--M [A] + M[B]
ADD R2, C, D			R2<--M [C] + M [D]
MUL X ,R1 ,R2		    M [X]<--R1 * R2

It is assumed that the computer has two processor registers, R 1 and R2. The symbol M [A] denotes the operand at memory address symbolized by A. The advantage of the three-address format is that it results in short programs when evaluating arithmetic expressions. The disadvantage is that the binary-coded instructions require too many bits to specify three addresses. An example of a commercial computer that uses three-address instructions is the Cyber 170. The instruction formats in the Cyber computer are restricted to either three register address fields or two register address fields and one memory address field.
Two-Address Instructions
Two-address instructions are the most common in commercial computers. Here again each address field can specify either a processor register or a memory word. The program to evaluate X = (A+B)*(C+D) is as follows:

MOV R1, A			R1<--M [A]
ADD R1, B			R1<--R1+M [B]
MOV R2, C			R2<--M [C]
ADD R2, D			R2<--R2+M [D]
MUL R1, R2			R1<--R1*R2
MOV X, R1			M [X]<--R1

The MOV instruction moves or transfers the operands t o and from memory and processor registers. The first symbol listed in an instruction is assumed to be both a source and the destination where the result of the operation is transferred.
One-Address Instructions
One-address instructions use an implied accumulator (AC) register for all data manipulation. For multiplication and division there is a need for a second register. However, here we will neglect the second register and assume that the AC contains the result of all operations. The program to evaluate X = (A+B)*(C+D) is

LOAD	A		    AC<--M[A]
ADD B			    AC<--AC+M[B]
STORE T			    M[T]<--AC
LOAD C			    AC<--M [C]
ADD D			    AC<--AC+M[D]
MUL T			    AC<--AC*M [T]
STORE X			    M[X]<--AC

All operations are done between the AC register and a memory operand. T is the address of a temporary memory location required for storing the intermediate result.
Zero-Address Instructions
A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack. The following program shows how X = (A + B) • (C + D) will be written for a stack organized computer. (TOS stands for top of stack.)

PUSH A 			TOS<--A
PUSH B 			TOS<--B
ADD 			TOS<--(A+B)
PUSH C			TOS<--C
PUSH D 			TOS<--D
ADD 			TOS<--(C+ D)
MUL 			TOS<--(C+D) * (A+B)
POP X 			M [X]<--TOS

To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression into reverse Polish notation. The name "zero-address" is given to this type of computer because of the absence of an address field in the computational instructions.


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