Answer Key and Solved Questions Paper-3 UGC-NET Computer Science December 2015
| 1. | The three outputs x1x2x3 from the 8x3 priority encoder are used to provide a vector address of the form 101x1x2x300. What is the second highest priority vector address in hexadecimal if the vector addresses are starting from the one with the highest priority? | ||||||||||
| A. | BC | ||||||||||
| B. | A4 | ||||||||||
| C. | BD | ||||||||||
| D. | AC | ||||||||||
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| 2. | WHAT WILL BE THE OUTPUT OF PORT1 IF THE FOLLOWING PROGRAM IS EXECUTED MVI B,82H MOV A,B MOV C,A MVI D,37H OUT PORT1 HLT | ||||||||||
| A. | 31 H | ||||||||||
| B. | 82H | ||||||||||
| C. | B9H | ||||||||||
| D. | 00H | ||||||||||
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| 3. | Which of the following 8085 microprocessor hardware interrupt has the lowest priority? | ||||||||||
| A. | RST 6.5 | ||||||||||
| B. | RST 7.5 | ||||||||||
| C. | TRAP | ||||||||||
| D. | INTR | ||||||||||
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| 4. | A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes? | ||||||||||
| A. | 0.64 | ||||||||||
| B. | 0.96 | ||||||||||
| C. | 2.00 | ||||||||||
| D. | 0.32 | ||||||||||
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| 5. | A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer? | ||||||||||
| A. | 0.06% | ||||||||||
| B. | 0.12% | ||||||||||
| C. | 1.2% | ||||||||||
| D. | 2.5% | ||||||||||
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| 6. | A CPU handles interrupt by executing interrupt service subroutine................. | ||||||||||
| A. | by checking interrupt register after execution of each instruction | ||||||||||
| B. | by checking interrupt register at the end of the fetch cycle | ||||||||||
| C. | whenever an interrupt is registered | ||||||||||
| D. | by checking interrupt register at regular time interval | ||||||||||
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| 7. | Given the following set of prolog clauses: father(X, Y): parent(X, Y), male(X), parent(Sally, Bob), parent(Jim, Bob), parent(Alice, Jane), parent(Thomas, Jane), male(Bob), male(Jim), female(Salley), female(Alice). How many atoms are matched to the variable ‘X’ before the query father(X, Jane) reports a Result? | ||||||||||
| A. | 1 | ||||||||||
| B. | 2 | ||||||||||
| C. | 3 | ||||||||||
| D. | 4 | ||||||||||
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| 8. | Forward chaining systems are ------------ where as backward chaining systems are------- | ||||||||||
| A. | Data driven,Data driven | ||||||||||
| B. | Goal Driven,Data driven | ||||||||||
| C. | Data driven,Goal Driven | ||||||||||
| D. | Goal Driven,Goal Driven | ||||||||||
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| 9. | Match the following w.r.t. programming languages:
Codes: (a) (b) (c) (d) | ||||||||||
| A. | (iii) (i) (ii) (iv) | ||||||||||
| B. | (i) (iii) (ii) (iv) | ||||||||||
| C. | (i) (iii) (iv) (ii) | ||||||||||
| D. | (ii) (iv) (i) (iii) | ||||||||||
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| 10. | The combination of IP Address and a port number is known as --------------- | ||||||||||
| A. | network number | ||||||||||
| B. | socket address | ||||||||||
| C. | subnet mask number | ||||||||||
| D. | MAC address | ||||||||||
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Author Does Not claim of any answer these answers are as per expert opinion
